1. Technical Field
This disclosure relates to semiconductor memory devices, and more particularly to flip-flop circuits having a test-input function and methods of latching data using pulses and according to normal and test operation modes.
2. Description of the Related Art
A semiconductor integrated circuit may include a plurality of flip-flops and each flip-flop latches data and outputs the latched data. Input and output operations of a flip-flop may be performed in synchronization with a clock signal. For example, the flip-flop may latch input data in synchronization with a rising edge of the clock signal and maintain the latched data until the next rising edge of the clock signal. Alternatively the flip-flop may latch input data in synchronization with a falling edge or in synchronization with both rising and falling edges.
A design-for-testability (DFT) technique is a design method adopted for enhancing and verifying the integrity of semiconductor chips. A scan test technique and a BIST (Built-in-Test) have been developed for practicing the DFT technique and are widely used to reduce the time it takes to test a semiconductor chip. In the scan test, a plurality of flip-flops form a scan chain, and the flip-flops function as a shift register. Almost all application-specific integrated circuits (ASICs) include a master-slave flip-flop of a multiplexer type to implement a test input function for the scan test.
FIG. 1 is a circuit diagram of a conventional master-slave flip-flop circuit, which is disclosed in U.S. Patent Application Publication No. 2006/0085709.
Referring to FIG. 1, a conventional master-slave flip-flop circuit 100 includes a first (master) latch 122, a second (slave) latch 124 and a (input) multiplexer 126.
The multiplexer 126 multiplexes a data signal D and a scan input signal SI based upon the value of a scan enable signal SE. The multiplexer 126 includes a first AND-gate 102 performing an AND operation upon the data signal D and an inverted scan enable signal ˜SE, a second AND-gate 104 performing an AND operation upon the scan input signal SI and the scan enable signal SE, and a NOR-gate 106 performing a NOR operation upon the outputs of the first and second AND-gates 102 and 104. The first latch 122 includes cross-connected inverters 110 and 112, and the second latch 124 includes cross-connected inverters 116 and 118. Each of the first and second latches 122 and 124 includes a tri-state inverter (112, 118) that is gated by a clock signal CK. Tri-state inverter 112 inverts the output of a first inverter 110 and applies the inverted signal to an input node of the first inverter 110 when the clock signal CK is in logic High level. Tri-state inverter 118 inverts the output of a second inverter 116 and applies the inverted signal to an input node of the second inverter 116 when the clock signal CK is in logic High level.
A tri-state inverter 108 is connected between the input multiplexer 126 and the first latch 122. The tri-state inverter 108 inverts the output of the NOR-gate 106 of the input multiplexer 126 and outputs the inverted signal when a clock signal CK is at a logic Low level. Tri-state inverter 114 inverts the output of the first inverter 110 and outputs the inverted signal when the clock signal CK is in logic Low level. A third inverter 120 inverts and amplifies the output of the second inverter 116.
When the scan enable signal SE is in logic Low state, the data signal D is transferred through the first AND-gate 102 and into the NOR-gate 106. In this case, when the clock signal CK is in logic Low level the first tri-state inverter 108 is turned ON and inverts the output of the NOR-gate 106 to transfer the inverted signal to the first latch 122, and when the clock signal CK is in logic High level the first tri-state inverter 108 is turned OFF and then first latch 122 stores the transferred data signal D. In the next cycle of the clock signal CK, when the clock signal CK is in logic Low level the third tri-state inverter 114 is turned ON and inverts the output of the first latch 122 to transfer the inverted signal to the second latch 124, and when the clock signal CK is in logic High level the third tri-state inverter 114 is turned OFF and the second latch 124 maintains the transferred data until the clock signal CK transitions subsequently.
As semiconductor integrated circuits become complicated, further limitations are added to the scan test and flip-flops capable of operating at high speed are required. The conventional flip-flop circuit 100 sequentially transfers data during each two cycles of the clock signal CK, thereby increasing delay in outputting data. In addition, the input multiplexer 126 for selecting the input of the master-slave flip-flop circuit 100 further increases the delay time since the data transfer path is prolonged. The master-slave flip-flops having such configurations are inadequate for high-speed semiconductor devices due to relatively large DtoQ delay between input and output of the flip-flop.